1. Field of the Invention
The present invention relates to a method of forming a metal-oxide semiconductor (MOS) transistor on a semiconductor wafer, and more particularly, to a lateral diffused metal-oxide semiconductor (LD MOS) transistor.
2. Description of the Prior Art
Metal-oxide semiconductor (MOS) transistors that consume less power and that can be highly integrated are widely used in the semiconductor industry. When a proper voltage is inputted, MOS transistors can be used as a kind of switch to control the flow of electricity through a device. In high voltage circuits, such as the input and output terminals of electrical equipment, LD MOS transistors are commonly used because of their ability to withstand heavy loads. As the development of integrated circuits progresses, controlling the manufacturing process of LD MOS transistors becomes an increasingly important issue.
Please refer to FIG. 1 to FIG. 6. FIG. 1 to FIG. 6 are cross-sectional diagrams of a method of forming a prior art LD MOS transistor 11. A semiconductor wafer 10 comprises a silicon substrate 12. In the method of forming the prior art LD MOS transistor 11, the semiconductor wafer 10 is first placed into a thermal oxidation furnace. A thermal oxidation process is performed to grow a silicon oxide layer 14, around 200 to 400 angstroms thick, on the surface of the silicon substrate 12. The silicon oxide layer 14 functions as a sacrificial oxide layer in a subsequent ion implantation process to increase the scattering of ions so as to prevent channeling. The silicon oxide layer 14 also functions as a pad oxide layer to promote the adherence between a subsequent silicon nitride layer and the silicon substrate 12.
A photoresist layer 16 is coated onto the semiconductor wafer 10, and a lithographic process is performed to define the ion implantation area of an n-well. An ion implantation process is performed to dope n-type dopants into the semiconductor wafer 10. Then the photoresist layer 16 is stripped. As shown in FIG. 2, the steps described above are performed again to form a photoresist layer 18 that defines the ion implantation area of a p-well adjacent to the n-well. Then p-type dopants are doped into the semiconductor wafer 10 and the photoresist layer 18 is stripped.
As shown in FIG.3, a thin film deposition process is performed using a chemical vapor deposition method to form a silicon nitride layer 20 on the silicon oxide layer 14. A lithographic process is performed to define the area which is predetermined for the formation of a field oxide layer. A dry etching process is then performed to remove the silicon nitride layer 20 in the predetermined area. Taking advantage of silicon nitride, which prevents diffusion of oxygen and water, the silicon nitride layer 20 is used as the mask in a local oxidation of silicon (LOCOS) process that forms the field oxide layer. As shown in FIG. 4, a wet oxidation process is performed to grow the field oxide layer 26 in the presence of water and oxygen, simultaneously using thermal diffusion to drive the p-type and n-type dopants into the silicon substrate 12 so as to form the p-well 22 and the n-well 24. The silicon nitride layer 20 is then stripped using a heated phosphoric acid solution.
As shown in FIG. 5, the gate oxide layer and the gate conductive layer of the LD MOS transistor are next formed. The residual silicon oxide layer 14 is removed completely using a wet etching process. Then, the silicon surface, which has suffered atmospheric exposure, is cleaned to ensure its quality. After the cleaning process, the semiconductor wafer 10 is placed into the thermal oxidation furnace again to form a silicon oxide layer 28, around 100 to 250 angstroms thick, on the active area using a dry oxidation process. A polysilicon layer 30, around 2000 to 3000 angstroms thick, is deposited onto the silicon oxide layer 28 using an LPCVD process. A thermal diffusion method or an ion implantation process is then performed to heavily dope the polysilicon layer 30 so as to reduce the resistivity of the polysilicon layer 30. The polysilicon layer 30 is utilized as a subsequent gate conductive layer 31 (FIG. 6). A lithographic process is performed to define a gate layer 38 using a photoresist layer 32.
Please refer to FIG. 6. A dry etching process is performed to remove both the polysilicon layer 30 and the silicon oxide layer 28 that are not within the area of the gate. The photoresist layer 32 is then stripped. The residual polysilicon layer 30 forms the gate conductive layer 31, and the residual silicon oxide layer 28 forms a gate oxide layer 29. Hence, the gate layer 38 comprises the gate oxide layer 29 and the doped polysilicon gate conductive layer 31. Also, the gate layer 38 is positioned on a portion of both the p-well 22 and the n-well 24, and one side of the gate layer 38 is positioned on the field oxide layer 26. A lithographic process and an ion implantation process are performed on the p-well 22 and the n-well 24 to form heavily doped n-type doped regions 34 and 36. The n-type doped region 34 is adjacent to one side of the gate layer 38 and the other n-type doped region 36 is adjacent to the field oxide layer 26. The n-type doped regions 34 and 36 function as the source and the drain of the LD MOS transistor.
In the method of forming the prior art LD MOS transistor 11, a portion of the silicon oxide layer 14 under the silicon nitride layer 20 will be oxidized due to the diffusion of water and oxygen during the thermal oxidation process of forming the field oxide layer 26. Consequently, a bird""s beak is formed in the region adjacent to the silicon nitride layer 20. Because the scale of the bird""s beak cannot be precisely controlled, the length of the field oxide layer 26 is also not of a precise length. In the prior art method, the n-type doped region 36, used as the drain, is positioned beside the field oxide layer 26, so the channel length, which is defined as the length from the source 34 to the drain 36 of the LD MOS transistor 11, is determined by the length of the field oxide layer 26. As a result, the on-resistance of the LD MOS transistor 11 cannot be precisely controlled, affecting the entire electrical performance of the LD MOS transistor.
It is therefore a primary objective of the present invention to provide a method of forming an LD MOS transistor on a semiconductor wafer to solve the above mentioned problem.
In a preferred embodiment, the present invention provides a method of forming an LD MOS transistor on a semiconductor wafer with a silicon substrate. An ion implantation process is performed on a predetermined area of the silicon substrate so as to form a p-well and an n-well, with the p-well adjacent to the n-well. A field oxide layer is formed to act as an insulation layer on a predetermined area of the n-well. A gate layer is formed on a portion of the p-well and the n-well, with one side of the gate layer positioned on the surface of the insulation layer. Finally, an ion implantation process is performed to form two doped regions on the p-well and the n-well. The two doped regions are used as the source and the drain of the LD MOS transistor.
It is an advantage of the present invention method that the channel length of the LD MOS transistor can be precisely controlled, so the on-resistance of the LD MOS transistor can also be well controlled. The p-well and the n-well of lower dosage dopants adjust the threshold voltage of the LD MOS transistor, and the region of higher dosage dopants enhances both the current, and the magnitude of the electrical field. Consequently, the present invention improves the electrical performance of the LD MOS transistor.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.